Embodiments of the present invention relate in general to cyclic redundancy codes (CRCs) and more specifically to using a CRC multiple-input shift register (MISR) to provide early warning and fail detection.
A CRC is an error-detecting code that is commonly used in digital networks and storage devices to detect errors in transmitted data. In transmissions involving packet or frame based protocols a CRC is often used to protect the data that is being carried within a packet or frame of bits. A short check value (e.g., a CRC) is attached to blocks of data entering these systems. The short check value is derived using contents of the data blocks and can be calculated, for example, based on the remainder of a polynomial division of the contents of the data blocks.
In many applications it is sufficient to simply use a CRC as a means of determining success or failure in delivering a frame from a source to a destination. However, in some applications it is desirable to know failure information about the packet, or frame. The need for additional failure information often leads to the use of more complex CRCs which provide either improved error rate detection and/or isolation metrics. In cases where applications are characterized as having high performance requirements, payload bandwidth can suffer from the presence of robust CRC protection because more CRC bits are required to provide more robust CRC protection and the ratio of payload bits to CRC bits in a frame transmission decreases. During system initialization, compromises are often made in balancing high bandwidth and reliability when selecting a level of CRC protection for transmitted data.